Planar transistors are often used to fabricate integrated circuit memory devices such as static random access memories (SRAM). A planar transistor has a diffused source electrode and drain electrode separated by a channel region. Overlying the channel region is a gate electrode that is separated from the channel region by a gate oxide. Planar transistors, although used and useful in many integrated circuit memory applications, are area intensive and consume a large amount of substrate area per transistor. In addition, with integrated circuit geometries decreasing into sub-micro ranges, planar transistors have various disadvantages. At smaller geometries and thinner gate oxide thicknesses, well documented problems such as hot carrier injection, leakage currents, isolation, short channel behavior, and channel length variations are major problems in planar transistors.
To overcome some of the disadvantages described above for planar transistors, thin film transistors (TFTs), elevated source and drain transistors, lightly doped drain (LDD) transistors, and other improvements were developed. Although the improvements reduced some of the disadvantages listed above, the improvements had some undesirable characteristics. The primary undesirable characteristic is the fact that the improved transistors were, in most cases, as area intensive or more area intensive than the planar transistor or, in the case of the TFT, did not perform as well as planar transistors. For example, small memory cell areas can result via the use of TFTs, but TFTs are highly resistive and therefore not adequate for all applications.
Various approaches have been used to try to reduce circuit surface area and increase transistor packing density while at the same time reducing some of the adverse effects described above. The surrounding gate transistor (SGT) was developed wherein a spacer gate and planar diffusions are used to form a transistor. The SGT reduced some of the disadvantages that affect planar transistors and reduced surface area due to a vertically positioned spacer gate. Topography problems and the geometry of the SGT usually result in source, gate, and drain contacts that are difficult to achieve and are difficult to consistently produce using submicron technology. In addition, doping of source regions, drain regions, and channel regions via implants can be difficult due to geometry and may require special processing.
Conventional planar transistors and TFT technology are not currently progressing at a rate which will allow for the formation of large memory cells, such as 64 Mbit SRAMs or 256 Mbit SRAMs.